Edge-NVMeVirt: Extending NVMeVirt for Edge Storage Research
Extended the NVMeVirt SSD emulator (FAST '23) to ARM edge platforms and DRAM-less SSDs.
Term project for Advanced Operating Systems (Spring 2026) at Seoul National University, with Hyunah Kim and Minsung Kim. NVMeVirt (FAST ‘23) is a software-defined NVMe device implemented as a Linux kernel module: it presents a virtual PCIe NVMe controller to the unmodified host driver, with FTL logic, NAND timing, and channel configuration all controllable in software. It was built, however, around x86 hosts and server-class SSDs — while edge platforms run on ARM-based SoCs and typically use DRAM-less SSDs, which cache only a small fraction of the logical-to-physical (L2P) mapping table in controller SRAM and borrow host DRAM through the NVMe Host Memory Buffer (HMB).
We extended it into Edge-NVMeVirt along both axes. On the host side, we ported NVMeVirt to ARM by replacing its x86-specific initialization path — reserving backing memory through the device tree instead of memmap=, building a software PCI-MSI interrupt domain in place of the APIC path, and separating MMIO and cacheable memory attributes. On the device side, we added a multi-tier SRAM/HMB/NAND translation cache that charges per-tier lookup latency on the critical path of every I/O, with latencies calibrated against a real DRAM-less SSD.
On a Jetson Orin Nano, Edge-NVMeVirt reproduces the characteristic behavior of the FORESEE XP1000 (a 128 GB DRAM-less SSD) — the HMB coverage cliff and its response to access locality — making it the first software-defined NVMe emulator to capture DRAM-less SSD behavior on edge platforms. It also exposes as tunable parameters what real hardware fixes, such as HMB size and the L2P cache replacement policy, opening a design space the physical device cannot explore.