High-Speed SHA-256 Accelerator
Designed the RTL of a SHA-256 hardware accelerator.
An undergraduate research internship under Prof. Deog-Kyoon Jeong.
I designed the RTL of a SHA-256 hardware accelerator in Verilog, implementing the full datapath and control logic. The design was optimized at multiple levels — from dataflow choices such as loop unrolling and quasi-pipelining down to logic- and gate-level refinements — to minimize end-to-end latency. I also carried out logic synthesis and a preliminary place-and-route pass using Synopsys Design Compiler / IC Compiler and Cadence Virtuoso.